Memory devices continue to scale to higher densities as the systems that use the memory increase in storage demands. Even as the amount of memory increases, there is an expectation that computing platforms such as servers, desktop or laptop computers, mobile devices, as well as consumer and business electronics will increase in performance. Increasing performance while also increasing memory size has resulted in increasing bandwidth scaling. The increased memory bandwidth scaling has required I/O (input/output) impedance compensation (ZQ comp) to be able to maintain adequate signal integrity. In previous generations of memory, different forms of resistance compensation or ZQ comp are primarily managed by the memory controller using modes in the memory devices (e.g., DRAM (dynamic random access memory)) to maintain a required tolerance. The modes refer to operating under different configuration settings.
As frequencies increase, the tolerance margins continue to increase in precision, and the overhead required of the memory controller in terms of its I/O interface idle period also continues to increase. The greater the overhead required of the memory controller, the more bandwidth is dedicated to managing the I/O tolerances, which can negatively impact performance. Traditional approaches to impedance compensation require the memory controller to periodically manage the I/O termination based on worst case system assumptions. In many cases it may not be required to perform an impedance compensation operation if the voltage and temperature of the memory devices are stable. More specifically, during an active period the operating conditions of temperature and voltage of the memory device could be reasonably stable and not require an impedance compensation adjustment. Thus, the memory controller would unnecessarily issue a ZQ comp signal to the memory devices. The unnecessary issuance of ZQ comp signals results in lower performance and increased complexity for the memory controller to manage multiple DRAM loads according to worst case where the DRAMs could operate with longer periods between adjustments.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.